JOB DESCRIPTION

Design Methodology, Engineer (KT)

Posting Date : 23 Oct 2018 | Close Date :22 Feb 2019


1.       Design Methodology, Engineer

Job responsibilities:

·         Work on timing and power Integrity design sign-off

·         Work closely with design team to schedule, prioritize and perform power integrity simulation for ARM/Imagination-based graphics processors, Modem and SoC

·         Involve in research and development work for advanced process node design methodology


 

Requirements

·         Bachelor/Masters Degree in Electrical/Computer Engineering

·         Min 5 years of high-speed CPU/GPU/DSP Subsystem RTL Integration experience or IP/Block/SoC Design experience. (Candidate with less than 5 years of relevant experience will be considered for junior position)

·         Experience in ARM/IMG/Tensilica Processor Familiarity, Silicon Debug and/or Functional/Direct Test Verification

·         Familiar with assertion based verification (SVA) & System Verilog language

·         Experience in Processor verification, FPGA verification and/or Formal verification

·         Experience with Synopsys ICC (preferred) or Cadence or Magma tools from netlists to GDS is a must

·         Experience in graphics processor implementation/power reduction flows and methodology from RTL to GDS (including synthesis, floor-planning, placement, CTS, routing, timing optimization, physical verification) is a plus

·         Knowledge of high-speed/low power IP and custom circuit design is a plus

·         Experience with power noise and reliability tools such as Redhawk and Voltus

·         Good communication and scripting skills

 

Interested applicants, please send your updated resume in MS WORD format to jialing@eps.com.sg for immediate processing. Do include your availability, last drawn & expected salary. We regret that only shortlisted candidates will be notified. Thank you.

Jia Ling l R1872250

 

 

Specialization : Engineering
Type of Employment : Permanent
Minimum Experience : 5
Work Location : West
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